Design Verification Engineerלוח משרות

Design Verification Engineer

קטגורית משרה 
הנדסת חשמל
מדעי המחשב
תיאור המשרה 
  • Develop detailed test and coverage plans based on the micro-architecture Develop verification methodology suitable for the IP, ensuring a scalable and portable environment.
  • Develop verification environment, including all the respective components such as stimulus, checkers, assertions, trackers, coverage.
  • Develop verification plans for all features under your care.
  • Execute verification plans, including design bring-up, DV environment bring- up, regression enabling all features under your care, and debug of the test failures. Develop block, IP and SoC level test-benches Track and report DV progress using a variety of metrics, including bugs and coverage


דרישות המשרה 
  • Deep knowledge of System Verilog and UVM
  • Advanced knowledge of System Verilog and UVM
  • Experience developing UVM based IP test-benches
  • Experience with complex designs and advanced debug skills ability
  • Experience with verification tools such as simulators, waveform viewers, build/run automation, coverage collection and analysis, gate level simulations
  • Experience with serial protocols such as PCIe or USB
  • Proven knowledge of one of the scripting languages: Python, Perl, TCL
  • In lieu of UVM knowledge, C/C++ experienced level knowledge
  • Lab hands-on debug
פרטי המפרסם
קישור חיצוני לאתר המפרסם 
מיקום המשרה
אזור בארץ