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Senior Verification Engineer

Cisco is looking for a Senior Verification Engineer to join the Front-End Design team at Cisco Silicon One, responsible for all chip design processes from definition and microarchitecture to final product.
Our design engineers engage in every aspect of chip design: definition, design, verification, signoff, and validation through to production.
We apply the latest silicon technologies and processes to build the largest-scale and most sophisticated devices, pushing the boundaries of feasibility.

Minimum Requirements:

  • 5+ years’ experience in digital logic design verification
  • Advanced knowledge of SystemVerilog and UVM
  • Advanced debug skills pre-silicon and in-lab

Preferred Requirements:

  • Scripting abilities
  • System integration knowledge (AMBA, PCIe. SPI, I2C, JTAG, CPU)
  • Basic SW knowledge (chop driver level)
  • Basic design knowledge

 Full-time position